RT-level sequential components

A register stores n bits from its n-bit data input I, with those stored bits appearing at its output Q.
A register has two control inputs clock and load.
For a rising edge triggered register the inputs I are only stored when load is 1 and clockis rising from 0 to 1.
The clock input is usually drawn as a small triangle, as shown in the figure.
Another common register control input is clear, which resets all bits to 0, regardless of the value of I.
Because all n bits of the register can be stored in parallel, we often refer to this type of register as a parallel-load register.

A shift register stores n bits, but these bits cannot be stored in parallel.
These bits are shifted into the register serially, meaning one bit per clock edge.
A shift register has a one-bit data input I, and at least two control inputs clock and shift.
When clock is rising and shift is 1,
The value of I is stored in the (n)’th bit.
The (n)’th bit is stored in the (n-1)’th bit.
The (n-1)’th bit is stored in the (n-2)’th bit.
and likewise, until the second bit is stored in the first bit.
The first bit is typically shifted out, meaning it appears over an output Q.

A counter is a register that can also increment (add binary 1) to its stored binary value.
A counter has a clear input, which resets all stored bits to 0.
It has a count input, which enables incrementing on the clock edge.
A counter often also has a parallel load data input and associated control signal.
A common counter feature is both up and down counting or incrementing and decrementing requiring an additional control input to indicate the count direction.
These control inputs can be either synchronous or asynchronous.
Asynchronous inputs are independent of the clock.
synchronous inputs are dependent of the clock.

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Author: Lakshmi Prasanna Ponnala

Completed M.Tech in Digital Electronics and Communication Systems. View all posts by Lakshmi Prasanna Ponnala