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Sequential custom single purpose processor design

• Combinational and sequential  logic  design   techniques   are   used   to   build   datapath   components and controllers.
• A sequential program   to   implement   computation  of  a  greatest  common  divisor   (GCD) is as follows.
• Figure 4.3(a) shows a black-box diagram of the desired system.
• Data inputs are: x_i and y_i
• data output d_o.

• The system’s functionality is straightforward: the output should represent the GCD of the inputs.
• If the inputs are 12 and 8, the GCD is 4.
• If the inputs are 13 and 5, the GCD is 1.
• Figure 4.3(b) provides a simple program with this functionality GCD.
• TO build a   single-purpose   processor   implementing the GCD program.
• To begin building our single-purpose processor implementing the GCD program.
• First convert our program into a complex state diagram, in which states and arcs may include arithmetic expressions.
• These expressions use  external  inputs  and   outputs or variables.
• In contrast, state  diagrams  includes  boolean   expressions, use external inputs and outputs,   not variables.
• Complex state diagram looks like a sequential program in  which  statements  are  scheduled   into states.
• Templates are to convert a program to a state diagram, as shown in Figure 4.2.
• Each statement can be  classified  into assignment  statement, loop  statement,  or branch (if-then-else or case) statement.

For assignment statement

• A state is created  with  the  statement  as  its   action. an arc is added from this state for the   next state.

For a loop statement

• For a loop statement, a condition state C and a join state J are created both with no actions.
• Add an arc with the loop’s condition from state C to the first statement in the loop body.
• Add a second  arc  from  !cond  to  the  next statement from the loop.
• Also add an arc from J to C.

For a branch statement

• For a branch statement, create a condition state C and a join state J, both with no actions.
• Create an arc  from  the  first  branch’s   condition(C1)  from  C  to  the  branch’s  first   statement(C1 stmts).
• Create another arc with the condition!(C1*C2) from C to C2 stmts.
• Repeat this for other branches.
• Finally, connect the  arcs  from  C1  stmts,  C2 stmts and others to J.
• Add an arc from J to next statement.
• Using this template  approach,  convert  GCD   program  to  the  complex  state  diagram  of   Figure 4.3(c).
• Now let us  see  the  designing  of  a  custom   single-purpose  processor  that  executes  the   GCD program.
• The next step is to divide the functionality into a datapath part and a controller part, as shown in Figure 4.4.
• The datapath interconnection of part should consist  of  an and combinational sequential components.
• The controller part should consist of a basic state diagram, i.e., one containing only boolean actions and conditions.

• Construct the datapath  through  a  four-step   process:
• 1. Create registers for declared variables. The variables are x and y. Create registers x and y and  connect  these  registers  to  input  ports.   create register d and connect it to the output   port.
• 2. Create a functional unit for each arithmetic operation in the state diagram. In the example, there are two subtractions, one comparison for   less  than,  one  comparison  for  inequality,   yielding two subtractors and two comparators.
• 3.Connect the ports, registers and functional units. A  source  may  be  an  input  port,  a functional unit, or another register.
• 4. Finally, create a unique identifier for each control input  and  output  of  the  datapath   components.
• Now that we have a complete datapath, we can build a state diagram for our controller.
• Figure 4.4 shows    the    controller   implementation model, and Figure 4.5 shows a   state table.
• Note that there are 7 inputs to the controller, resulting in 128 rows for the table.

• don’t cares are used to reduce the rows in the state table for some input combinations, still   optimization is possible by using (CAD) tools.

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RT-level sequential components

• For complex sequential  systems,abstract sequential components are used.
• The components are:
• Register
• Shift register
• Counter

Register

• A register stores n bits from its n-bit data input I, with those stored bits appearing at its output Q.
• A register has two control inputs clock and load.
• For a rising edge triggered register the inputs I are only stored  when  load  is  1  and  clockis rising from 0 to 1.
• The clock input is usually drawn as a small triangle, as shown in the figure.
• Another common  register  control  input  is clear, which resets all bits to 0, regardless of the value of I.
• Because all n bits of the register can be stored in parallel, we  often  refer  to  this  type  of register as a parallel-load register.

Shift Register

• A shift register  stores  n  bits,  but  these  bits cannot be stored in parallel.
• These bits are shifted into the register serially, meaning one bit per clock edge.
• A shift register has a one-bit data input I, and at least two control inputs clock and shift.
• When clock is rising and shift is 1,
• The value of I is stored in the (n)’th bit.
• The (n)’th bit is stored in the (n-1)’th bit.
• The (n-1)’th bit is stored in the (n-2)’th bit.
• and likewise, until the second bit is stored in the first bit.
• The first bit is typically shifted out, meaning it appears over an output Q.

Counter

• A counter is a register that can also increment (add binary 1) to its stored binary value.
• A counter has  a  clear  input,  which  resets  all stored bits to 0.
• It has a  count  input,  which  enables incrementing on the clock edge.
• A counter often  also  has  a  parallel  load  data input and associated control signal.
• A common counter feature is both up and down counting or incrementing  and  decrementing requiring an additional control input to indicate the count direction.
• These control inputs can be either synchronous or asynchronous.
• Asynchronous inputs are  independent  of  the clock.
• synchronous inputs are dependent of the clock.

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Sequential logic design

• A sequential circuit is a digital circuit whose outputs are a function of the current as well as previous input values.
• Sequential logic possesses memory.
• One of the most basic sequential circuits is the flip-flop.
• A flip-flop stores a single bit.

D-Flip-Flop

• The simplest type  of  flip-flop  is  the  D  flip- flop.
• It has two inputs: D and clock.
• When clock is 1, the value of D is stored in the flip-flop output Q.
• When clock is 0, the value of D is ignored; the output Q maintains its value.

SR-Flip-Flop

• An SR flip-flop has threee inputs S,R,clk
• S stands for Set and R stands for Reset.
• When clock is  0,  the  previously  stored  bit  is maintained and appears at output Q.
• When clock is  1,  the  inputs  S  and  R  are examined.
• If S is 1, 1 is stored in Q.
• If R is 1 , 0 is stored in Q.
• If both are 0s there is no change
• If bothe are 1s behavior is undefined.

JK-Flip-Flop

• An JK flip-flop has three inputs J,K,clk
• JK flip-flop is same as  that  of  SR  flip-flop except that when J and K are 1, the stored bit toggles from 1 to 0 or 0 to 1.
• When clock is  1,  the  inputs  J  nad  K  are examined .
• If J is 1, 1 is stored in Q.
• If K is 1 , 0 is stored in Q.

• If both are 0s there is no change
• If bothe are 1s output toggles.

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RT level Combinational Components

• A large combinational circuit would be very complex to design.
• For example, a circuit with 16 inputs would have 2^16, or 64K, rows in its truth table.
• One way to reduce the complexity is to use combinational components instead of logic gates.
• Such combinational components often called Register-Transfer (or) RT-level components.

Multiplexer

• A multiplexor, sometimes called a selector, allows only one of its data inputs Im to pass through to the output O.
• Allowing only one of multiple input tracks to connect to a single output track.
• If there are m data inputs, then there are log2(m) select lines S, and an mX1 multiplexer has m data inputs, one data output.
• For Example an 8X1 Mux has 8- input lines and 1-output line and 3 select lines.
• The binary value of S determines which data input passes through;
• 00…00 means I0 may pass,
• 00…01 means I1 may pass,
• 00…10 means I2 may pass, and so on.
• For example, an 8×1 multiplexor has 8 data inputs and thus 3 select lines.
• If s =110, then I6 will pass through to the output. So if I6 is 1, then the output would be 1; if I6 is 0, then the output would be 0.
• Commonly n-bit multiplexer is used which is a more complex device.
• Each data input and output, consists of n bits( lines).
• For Example, a 4-bit 8×1 multiplexer. Thus, if I6 were 0110, then the output would be 0110.
• n is independent of the number of select lines.

Decoder

• A decoder is another combinational circuit.
• A decoder converts its binary input I into a one-hot output O.
• “One-hot” means that exactly one of the output lines can be 1 at a given time.
• A decoder nX2^n has n-inputs and 2^n outputs.
• A decoder can also be specified log2(n) x n where log2(n) number of inputs and n represents number of outputs.
• For example, a 3×8 decoder has 3 inputs and 8 outputs.
• If the input is 000, then the output O0 would be 1.
• If the input is 001, then the output O1 would be 1, and so on.
• An extra input is enable, when enable is 0 all outputs are O. When enable is 1, the decoder functions as before.

Adder

• An adder adds two n-bit binary inputs A and B, generating an n-bit output sum along with an output carry.
• For example, a 4-bit adder would have a 4-bit A input, a 4-bit B input, a 4-bit sum output, and a 1-bit carry output.
• If A is 1010 and B is 1001, then sum would be 0011 and carry would be 1.
• An adder often comes with a carry input also, such adders can be cascaded to create larger adders.

Comparator

• A comparator compares two n-bit binary inputs A and B, generating outputs.
• Output indicating whether A is less than, equal to, or greater than B.
• If A were 1010 and B were 1001, then less would be 0, equal would be 0, and greater would be 1.

ALU

• An ALU (arithmetic-logic unit) can perform a variety of arithmetic and logic functions on its n-bit inputs A and B.
• The select lines S choose the current function.
• If there are m possible functions, then there must be at least log2(m) select lines.
• Common functions include addition, subtraction, AND, and OR.

Shifter

• Another common RT-level component is a shifter.
• An n-bit input I can be shifted left or right and then output to an output O.
• For example, a 4-bit shifter with an input 1010 would output 0101 when shifting right one position.
• Shifters come with an additional input indicating what value should be shifted in and an additional output indicating the value of the bit being shifted out.

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Basic Combinational Logic Design

• A combinational circuit is a digital circuit whose output is purely a function of its current inputs.
• It has no memory(past inputs).
• A simple technique is used to design a combinational circuit using basic logic gates.
• Step1:- Problem description(output in terms of inputs).
• Step2:- Translation of description into truth table with all possible input configurations.
• Step3:- Derivation of output equations from output columns.
• Step4:- Minimization of output equations by using k-maps to minimize the number of logic gates.
• Step5:- Obtaining the final circuit from the output equations.

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Combinational logic design

• A transistor is the basic electrical component of digital systems.
• Combinations of transistors forms logic gates.
• Logic gates are the basic building block of digital systems.
• A transistor acts as a simple on/off switch.
• One type of transistor is CMOS transistor.
• n-MOS transistor is shown in Fig 4.1(a).
• The gate controls whether or not current flows from the source to the drain.
• When a high voltage (typically +5 Volts, which we’ll refer to as logic 1) is applied to the gate, the transistor conducts, so current flows.
• When low voltage (or) logic 0 is applied to the gate, the transistor does not conduct.

• Fig 4.1(c) shows an Inverter.
• When the input x is logic 0, the top transistor conducts (and the bottom does not), so logic 1 appears at the output F.
• When the input x is logic 0, then output becomes 1.

• Fig 4.1(d) shows NAND gate.
• x, y are inputs to NAND gate and F is the output.
• When at least one of the inputs x and y is logic 0, then at least one of the top transistors conducts (and the bottom transistors do not), so logic 1 appears at F.
• If both inputs are logic 1, then neither of the top transistors conducts, both of the bottom transistors conducts so logic 0 appears at F.

• Fig 4.1(e) shows NOR gate.
• When two inputs are at logic 0, then output F is 1.
• When two inputs are at logic 1, then output F is 0.

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Custom Single Purpose Processors

Introduction:-

• A single-purpose processor is a digital system intended to solve a specific computation task.
• A manufacturer builds a standard single-purpose processor for use in a variety of applications.
• A custom single purpose processor to execute a specific task within our embedded system.
• Benefits of a custom single purpose processor are:
• performance is fast, due to fewer clock cycles.
• It consists of simpler functional units, less multiplexers, or simpler control logic.
• size is small, due to a simpler datapath.
• No program memory.
• Less NRE cost.
• Reduced performance and size.

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