Pseudo Noise Sequences (PN Sequences)

Pseudo Noise Sequences (PN Sequences):-

A PN Sequence is a periodic binary sequence with a noise like wave form (generally of high frequency) .

PN Sequences are commonly used to generate noise that is approximately “white”.

It has applications in scrambling, cryptography and spread spectrum communications.

It is commonly referred to as Pseudo Random Binary Sequence (PRBS) and they are widely used in communication standards these days.

The qualifier “Pseudo” implies that the sequence is not truly random. Actually, it is periodic with a large period and exhibits some characteristics of a random white sequence with in that period.

Generation of PN Sequences:-

PN Sequence is a periodic noise like wave form that is usually generated by means of a feedback shift Register, a general Block Diagram of which is shown below.

  1. A feedback Shift register consists of an ordinary shift register made up of ‘m’ no. of Flip-flops.(two state memory stages) 1,2,3….m. The data of one FF is shifted to the next FF whenever a clock pulse is applied and a logic circuit that are inter connected to form a multi loop feedback circuit.
  2. The FF’s in the shift register are regulated by a single timing clock. at each pulse (clock) of the clock, the state of each FF is shifted to the next one down the line.
  3. With each clock pulse the logic circuit computes a Boolean function of the states of the FF’s the result is then feedback as the i/p to the first FF, thereby preventing the shift register from emptying.

The PN Sequence so generated is determined by the length ‘m’ of the shift registers its initial state and the feedback logic.

Let  S_{j}(k) denote the state of the j^{th} FF after   clock pulse. This state may be represented by ‘0’ (or) ‘1’. The state of the shift register after the k^{th}  clock pulse is then defined by the set { S_{1}(k),S_{2}(k),S_{3}(k),....S_{m}(k) } where k\geq 0.

For the initial state, k is zero.

From the definition of a shift register.

S_{j}(k+1)=S_{j-1}(k),\left\{\begin{matrix} k\geq 0.\\ 1\leq j\leq m. \end{matrix}\right.

Where  S_{o}(k)  is the  i/p applied to the first Flip-Flop after  k^{th} clock pulse. According to the configuration described e  S_{o}(k) is a Boolean function of the individual states S_{1}(k),S_{2}(k),S_{3}(k),....S_{m}(k).

For a specified length m this Boolean function uniquely determines the subsequence sequence of states and therefore the PN Sequence produced at the o/p of the final Flip-Flop in the shift register.

With ‘m’ no . of FF’s no. of possible states of the shift register is at most 2^{m} .

Therefore the PN Sequence generated by a feedback shift register must eventually become periodic with a period of at most t 2^{m} 

A feedback shift register is said to be linear when the feedback logic consists of entirely modulo-2 (EX-OR gates) adders.

A zero state is not permitted because (i.e, a state with all FF’s set to zero) the shift register remains in the same state forever.

The period of a PN Sequence produced by a linear feedback shift register with ‘m’ Flip Flops can not exceed    \ngtr (2^{m}-1).

When the period is exactly (2^{m}-1) , the PN Sequence is called a Maximal length Sequence  (or) m-Sequence.




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Author: vikramarka

Completed M.Tech in Digital Electronics and Communication Systems and currently working as a faculty.